As electronic devices bus widths and bus speeds increase, the components that drive those busses must accommodate ever more accurate timing constraints. The use of PLL (phase locked loop) and/or DLL (delay locked loop) circuits assists in meeting those constraints.
PLL and/or DLL circuits often are used to assist in aligning clocks with respect to other signals (e.g. data, etc.). The offsets (e.g. static offsets) in PLL and/or DLL circuits are fixed and may not allow optimum device (e.g. component) performance. This may present a problem.